Patent · US Active

Systems and methods for CPU repair

US8667324B2 · kind B2 · utility

0Cited by

34References

21Claims

0Family size

Assignee

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. · US

Inventors

Jeff Barlow · Roseville, US
Jeff Brauch · Fort Collins, US
Howard Calkin · Davis, US
Raymond Gratias · Fort Collins, US
Stephen Hack · Fort Collins, US
Lacey Joyal · Fort Collins, US
Guy Kuntz · Chico, US
Ken Pomaranski · Roseville, US
Michael Sedmak · Fort Collins, US

Key dates

Filing date	Feb 17, 2006
Grant date	Mar 4, 2014
Priority date	—
Expiry date	Feb 22, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/121
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.