Frame boundary detection and synchronization system for data stream received by ethernet forward error correction layer
US8667373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2010 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Mar 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.