Flat panel display and method for making the same
US8669136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2011 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Nov 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/122
Abstract
A flat panel display includes a thin film transistor formed on a substrate; a planarization layer formed on the thin film transistor; a first electrode layer formed on the planarization layer and electrically connected with the thin film transistor through the via hole formed in the planarization layer; a pixel definition layer formed on the planarization layer and in which an opening for at least partially exposing the first electrode layer is formed; an adhesive reinforcement layer formed at least between the planarization layer and the pixel definition layer on the top of the planarization layer; an emitting layer formed on the first electrode layer; and a second electrode layer formed on the emitting layer and the pixel definition layer. The flat panel display has an improved adhesive property between a pixel definition layer and a planarization layer, which prevents a chipping phenomenon of the pixel definition layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.