Methods and apparatus for non-volatile memory cells with increased programming efficiency
US8669607B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2012 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Nov 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.