Flat display and timing controller thereof for neutralizing charges in liquid crystal capacitors upon shut down
US8669974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2007 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Apr 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/027
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A timing controller adapted to a flat display includes a voltage detecting circuit, a clock generator, a first multiplexer and a second multiplexer. The voltage detecting circuit detects a variation of an operating voltage and thus outputs a reset signal. The clock generator outputs a start signal and a first clock signal. The first multiplexer is controlled by the reset signal and coupled to the start signal and a constant voltage. The second multiplexer is controlled by the reset signal and coupled to the first clock signal and a second clock signal. A frequency of the second clock signal is obviously higher than a frequency of the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.