Data holding device
US8670263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2011 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Jan 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NAND3 and NAND4) connected in a loop, a nonvolatile storage portion (NVM) for storing in a nonvolatile manner the data held in the loop structure portion (LOOP) by using the hysteresis characteristics of ferroelectric elements, a circuit separating portion (SEP) for electrically separating the loop structure portion (LOOP) and the nonvolatile storage portion (NVM), and a set/reset controller (SRC) for generating a set signal (SNL) and reset signal (RNL) based on data stored in the nonvolatile storage portion (NVM), wherein the plurality of logic gates are each set and reset to an arbitrary output logic level in accordance with the set signal (SNL) and reset signal (RNL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.