Circuit simulation system with repetitive algorithmic choices that provides extremely high resolution on clocked and sampled circuits
US8670969B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Dec 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for eliminating the Fourier analysis noise floor generated by a circuit simulator is disclosed. This is accomplished by making the simulator behavior during each Fourier analysis sample interval (704) algorithmically identical to that employed during every other sample interval. Thus between each Fourier analysis sample point (703), the step size, number of iterations, integration method, etc., are allowed to vary as needed with the proviso that each sample interval uses exactly the same sequence of time steps, and that each member of that sequence is algorithmically identical to the corresponding members in the sequences used on every other Fourier sample interval. In other words, the first time step in the first interval must be algorithmically identical to the first time step in every other interval. The same is true for the second step, the third step, and so on until the last step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.