Computer bus with enhanced functionality
US8671236B2 · kind B2 · utility
5Cited by
6References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2011 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Mar 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.