Systems and methods for configuration of control logic in parallel pipelined hardware
US8671371B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2012 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph comprises a data path to be implemented in hardware as part of said stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned to divide it into a plurality of discrete regions. Discrete control logic elements are assigned to each region using high level synthesis. The graph and assigned control logic is used to define a hardware design for the pipelined parallel stream processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.