Functional timing analysis method for circuit timing verification
US8671375B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2012 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Nov 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A functional timing analysis method, executed in a computing device, comprises: step A: obtaining a circuit; step B: selecting a target delay time from a delay time set for a node in the circuit for verifying whether the target delay time is attainable by some input assignment; step C: generating a timed characteristic function associated with the selected target delay time for the node recursively from the timed characteristic functions associated with the corresponding delay times for its fanin nodes is generated as a target formula; step D: recursively translating the timed characteristic function into timed characteristic function clauses of the target formula by using an implication operator; step E: checking whether the target formula is satisfied by using a Boolean satisfiability solver; and step F: if the target formula is satisfied, the selected target delay time is attainable by some input assignment to the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.