Method and apparatus for back end of line semiconductor device processing
US8673765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Jun 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). The inter-metal dielectric (IMD) layer between two metal layers may comprise an etching stop layer over a metal layer, a low-k dielectric layer over the etching stop layer, a dielectric hard mask layer over the low-k dielectric layer, an nitrogen free anti-reflection layer (NFARL) over the dielectric hard mask layer, and a metal-hard-mask (MHM) layer of a thickness in a range from about 180 Å to about 360 Å over the NFARL. The MHM layer thickness is optimized at the range from about 180 Å to about 360 Å to reduce the Cu pits while avoiding the photo overlay shifting issue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.