Method for manufacturing semiconductor device having interlayer dielectric layers and a gate contact
US8673776B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Jan 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device comprises: providing a substrate having an active area and a gate structure on the active area and formed with a first interlayer dielectric layer thereon, wherein the first interlayer dielectric layer has a first open to expose a portion of a surface of the active area, and an upper surface of the first interlayer dielectric layer is substantially flush with an upper surface of the gate; filling the first open with a first conductive material to form a first portion of contact; forming a second interlayer dielectric layer over the first interlayer dielectric layer, the second interlayer dielectric layer having a second open to substantially expose an upper part of the first portion of the contact in the first open; and filling the second open with a second conductive material to form a second portion of the contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.