Fractional phase-locked loop with dynamic divide ratio adjustment
US8674731B1 · kind B1 · utility
6Cited by
5References
28Claims
0Family size
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Key dates
| Filing date | Jan 22, 2013 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Jan 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.