Patent · US Active

Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter

US8674862B1 · kind B1 · utility

7Cited by
1References
23Claims
0Family size

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Key dates

Filing dateSep 5, 2012
Grant dateMar 18, 2014
Priority date—
Expiry dateSep 5, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03M1/804
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

Systems and methods of calibrating a successive approximation register analog-to-digital converter (ADC) are disclosed. A plurality of capacitor stages, a first capacitor array, and a first capacitor stage are coupled in parallel. A capacitance of the first capacitor stage is compared to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array. In response to the comparing, the capacitance of the first capacitor stage is increased by increasing the capacitance of a second capacitor array if the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.