Low noise memory array
US8675395B2 · kind B2 · utility
Inventor
Key dates
| Filing date | May 22, 2013 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | May 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region (850,852) is formed in the substrate. The trench isolation region has sides and a bottom formed below a face of the substrate. A first semiconductor region having a second conductivity type (868) is formed at the bottom of the trench isolation region. A second semiconductor region having the second conductivity type (870) is formed separately from the first semiconductor region adjacent a first side of trench isolation region and in conductive contact with the first semiconductor region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.