Control of processor cache memory occupancy
US8677071B2 · kind B2 · utility
19Cited by
9References
43Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Mar 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.