Low-power multi-standard cryptography processing units with common flip-flop/register banks
US8677150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2012 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Feb 2, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and apparatus for managing a plurality of cipher processor units. A cipher module may receive a cipher instruction indicating a cipher algorithm to be used. The cipher module may identify a cipher processing unit of the plurality of cipher processing units associated with the cipher algorithm. The cipher module may execute the cipher instruction using the cipher processing unit and the common register array. The cipher module may store a state of a common register array to be used by the cipher processing unit of the plurality of cipher processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.