Method and system for decoding
US8677227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | May 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6577
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.