Method and system for model-based design and layout of an integrated circuit
US8677301B2 · kind B2 · utility
6Cited by
40References
20Claims
0Family size
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Key dates
| Filing date | Jun 27, 2012 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Jun 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.