Method and system for implementing die size adjustment and visualization
US8677307B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Sep 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are improved methods, systems, and computer program products for visualizing and estimating IC die arrangement for an electronic design, and for performing chip planning and estimation based upon the estimated and visualized IC die arrangements. According to some approaches, an interface is provided for visualizing different die arrangement options for an electronic design, in which a filmstrip view is provided to display smaller images of different die arrangement options, and a central viewing area is provided to view a larger image of a selected candidate die arrangement. The different images, whether smaller or larger images, are maintained with design object information and not just static images. This allows for selection and highlighting of individual objects within the die arrangement images, as well as corresponding highlighting of that same object in other images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.