Semiconductor memory device
US8680505B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2013 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/20
Abstract
A semiconductor memory device, including: plural parallel first lines; plural second lines disposed to intersect the first lines; and a memory cell array including memory cells, disposed at intersections of the first lines and the second lines, each of the memory cells configured by a rectifier element and a variable resistor connected in series. The rectifier element includes: a first semiconductor region including an impurity of a first conductivity type at a first impurity concentration; and a second semiconductor region including an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration and including an impurity of the first conductivity type at a third impurity concentration lower than the second impurity concentration, the first and second semiconductor regions being formed by silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.