Nonvolatile semiconductor memory device and method of manufacturing the same
US8680604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Jun 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
Abstract
A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.