Depletion mode semiconductor device with trench gate and manufacturing method thereof
US8680609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2011 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Sep 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.