Facet-free semiconductor device
US8680625B2 · kind B2 · utility
10Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | May 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.