PFC booster circuit
US8680820B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power factor correction booster circuit for connection to an alternating current (AC) power source including a first circuit portion arranged to be active over a first AC half cycle of the power source, the first circuit portion including: a first AC input node in connection with a source node of a first power transistor, a first node of an inductive element in connection with a drain node of the first power transistor, a second node of the inductive element in connection with a drain node of a second power transistor, a second AC input node in connection with a source node of the second power transistor, an anode of a first semiconductor diode element in connection with the second node of the inductive element, a cathode of the first semiconductor diode element in connection with a first node of a first output capacitor element, and a second node of the first output capacitor element in connection with the second AC input node, wherein the first and second power transistors are controllable to switch the first circuit portion between a forward mode and a flyback mode, such that in the forward mode the inductive element stores energy from the AC power source, and in the flyback m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.