Amplification circuit comprising input signal limiting network
US8680926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2012 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Aug 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/555
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an integrated amplification circuit for a transducer signal comprising a semiconductor substrate. The semiconductor substrate comprises a signal limiting network comprising first and second parallel legs coupled between an input of a preamplifier and a first predetermined electric potential of the integrated amplification circuit. The first leg comprises a plurality of cascaded semiconductor diodes coupled to conduct current in a first direction through the limiting network and the second leg comprises a plurality of cascaded semiconductor diodes coupled to conduct current in a second direction through the limiting network. A current blocking member is configured to break a parasitic current path between an anode or a cathode of a semiconductor diode of the first leg or the second leg and the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.