Size and retry programmable multi-synchronous FIFO
US8681526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2008 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Jun 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of addressable memory locations; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions to write to one or more of the selected number of addressable memory locations; and selectable transaction retry control means configured to cause read control means to repeat selected pop transactions and/or cause write control means to repeat selected push transactions. In another embodiment a method of retrying a transaction in a multi-synchronous FIFO having a selectable number of addressable memory locations generally comprises the steps of receiving a transaction request; storing the starting address of the transaction register in a start register; executing the transaction; incrementing the starting address in the transaction register after comparing the incremented address to the selected numb…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.