Training a memory controller and a memory device using multiple read and write operations
US8681571B2 · kind B2 · utility
8Cited by
26References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Jun 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a memory controller to a memory device. A second calibration operation may be associated with second data read at the memory controller from the memory device. The operating parameter may be set based on a result of at least one of the first and the second calibration operations at the memory device or the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.