Single wire bus communication protocol
US8683101B2 · kind B2 · utility
6Cited by
11References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Apr 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of communication over a single-wire bus between a transmitter device and at least one receiver device, wherein each data bit is transmitted in a frame successively including: a synchronization slot different from a reference voltage of the devices; a first idle slot in a state corresponding to the reference voltage of the circuit; a slot representing the data bit to be transmitted; a second idle slot identical to the first one; a slot intended to contain the state of an optional response bit; and an end slot identical to the idle slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.