Method and system for fast two bit error correction
US8683293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2009 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Apr 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.