Patent · US Active

Method and system for optimizing placement of I/O element nodes of an I/O ring for an electronic design

US8683412B1 · kind B1 · utility

1Cited by

35References

36Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Thaddeus Clay McCracken · Portland, US
Miles P. McGowan · San Jose, US

Key dates

Filing date	Dec 23, 2010
Grant date	Mar 25, 2014
Priority date	—
Expiry date	Mar 5, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.