Power domain crossing interface analysis
US8683419B1 · kind B1 · utility
17Cited by
5References
25Claims
0Family size
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Key dates
| Filing date | Nov 30, 2012 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Nov 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided to test an integrated circuit design for power management circuit design errors comprising: configuring a computer to identify multiple power domain crossing paths between pairs of power domains; identify one or more power related constraints associated with such power domain crossing paths; and group power domain crossing paths between matching power domain pairs that are associated with matching power related constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.