Semiconductor memory device and method for manufacturing the same
US8686387B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Sep 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
Abstract
A semiconductor memory device includes a cell array layer having a memory cell. The memory cell has a current control device, a variable resistance device and a metal layer for silicide. A method for manufacturing the semiconductor memory device includes: forming the metal layer for silicide on a semiconductor layer for forming the current control device and a variable resistance device layer; selectively removing the variable resistance device layer and the metal layer through first etching; forming a first protective layer to cover at least a side surface of the metal layer exposed by the first etching; selectively removing a part of the semiconductor layer, through second etching; and forming a second protective layer to cover the variable resistance device layer, the metal layer for silicide, and the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.