Semiconductor device
US8686392B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Aug 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor device includes a memory cell including a plurality of magnetoresistive elements disposed therein, and a peripheral circuit region disposed around the memory cell region. The magnetoresistive element includes a magnetization fixed layer, a magnetization free layer, and a tunneling insulation layer. The semiconductor device includes, above the magnetoresistive elements, a plurality of first wires extending in the direction along the main surface. In the peripheral circuit region, there is disposed a multilayer structure of lamination of a layer equal in material to the magnetization free layer, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer so as to overlap a second wire formed of the same layer as the first wire in plan view. The multilayer structure does not overlap both of a pair of adjacent second wires in plan view in the peripheral circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.