Memory device

US8686486B2 · kind B2 · utility

Assignee

• Semiconductor Energy Laboratory Co., Ltd. · JP

Inventors

• Kiyoshi Kato · Yokohama, JP
• Toshihiko Saito · Yokohama, JP

Key dates

• Filing date: Mar 21, 2012
• Grant date: Apr 1, 2014
• Expiry date: Mar 21, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.