Lateral high-voltage transistor and associated method for manufacturing
US8686503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Apr 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
The present disclosure discloses a lateral high-voltage transistor and associated method for making the same. The lateral high-voltage transistor comprises a semiconductor layer of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer separated from the source region; a first isolation layer atop the semiconductor layer between the source region and the drain region; a first well region of the second conductivity type surrounding the drain region, extending towards the source region and separated from the source region; a second well region of the first conductivity type surrounding the source region; a gate positioned atop the first isolation layer above the second well region and an adjacent portion of the first well region; and a first buried layer of the first conductivity type under the first well region adjacent to the source region side of the lateral high-voltage transistor. A JFET is formed using the gate as a JFET top gate and the first buried layer as a JFET bottom gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.