System and method for I/O ESD protection with floating and/or biased polysilicon regions

US8686507B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Ting Chieh Su · Nantou, CN
• Min-Chie Jeng · Taipei, TW
• Chin Chang Liao · Shanghai, CN
• Jun Cheng Huang · Shanghai, CN

Key dates

• Filing date: Sep 6, 2006
• Grant date: Apr 1, 2014
• Expiry date: Feb 19, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.