Latency tolerant system for executing video processing operations
US8687008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Dec 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/86
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.