Signal processing device, integrated circuit, control program, and computer readable recording medium
US8687124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2010 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Nov 8, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/213
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A signal processing device (201) includes noise reduction units (101), cascade-connected to each other, each of which includes: a signal selection section (31) for selecting a representative value from sampled signals obtained from an input signal by sampling a target signal and signals which are away from the target signal by given intervals; a voltage determination section (51) for determining which of a determined representative value and a voltage of the target signal is larger; and a signal output section (61) for increasing or decreasing the voltage of the target signal depending on a result of the determining and outputs the target signal as the output signal. A combination of intervals between the target signal and the signals excluding the target signal vary from noise reduction unit (101) to noise reduction unit (101). A noise reduction unit on a more upstream side has a larger maximum value of the intervals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.