Semiconductor device and structure
US8687399B2 · kind B2 · utility
7Cited by
323References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Apr 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An Integrated device comprising a first monocrystalline layer comprising logic circuit regions and a second monocrystalline layer comprising memory regions constructed above first monocrystalline layer, wherein the memory regions comprise second transistors, wherein said second transistors comprise drain and source that are horizontally oriented with respect to the second monocrystalline layer, and a multiplicity of vias through the second monocrystalline layer providing connections between the memory regions and the logic circuit regions, wherein at least one of the multiplicity of vias have a radius of less than 100 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.