Delay matching across semiconductor devices using input/output pads
US8687442B1 · kind B1 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Nov 8, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Aug 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data signal is sampled by generating a read enable signal at a first semiconductor device which is intended for a second semiconductor device. A read enable signal with at least some I/O pad delay included is obtained, including by passing the read enable signal intended for the second semiconductor device at least partially through an input/output (I/O) pad on the first semiconductor device. At the first semiconductor device, a data signal from the second semiconductor is sampled using the read enable signal with at least some I/O pad delay included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.