Semiconductor device and manufacturing method thereof
US8687444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Apr 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of memory cells are tested in order. Each time a defective memory cell is detected by the test, error pattern information is updated based on a relative arrangement relationship between a plurality of defective memory cells, and error address information is updated based on the addresses of at least part of the plurality of defective memory cells. According to the present invention, it is possible to significantly reduce the storage capacity of the analysis memory. This allows the implementation of the analysis memory itself in the semiconductor device, in which case external testers need not include the analysis memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.