Energy efficient processor having heterogeneous cache
US8687453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.