Method and system for ordering posted packets and non-posted packets transfer
US8687639B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2009 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Jul 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for ordering packets. The system includes a first memory, e.g., FIFO, storing transition information for posted packets, e.g., 1 when a posted packet transitions from a non-posted packet and 0 otherwise. A second memory stores transition information for non-posted packets, e.g., 1 when a non-posted packet transitions from a posted packet and 0 otherwise. A counter increments responsive to detecting a transition in the first memory and decrements responsive to detecting a transition in the second memory. A controller orders a posted packet for transmission prior to a non-posted packet if a value of the counter is negative and when a transitional value associated with the non-posted packet is 1, and wherein the controller orders either a posted packet or a non-posted packet otherwise. The first and the second memory may be within a same memory component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.