Method, apparatus and full-system simulator for speeding MMU simulation
US8688432B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2008 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Jul 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.