Computer peripheral expansion apparatus
US8688887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2009 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Dec 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.