System and method for increasing DDR memory bandwidth in DDR SDRAM modules
US8688892B2 · kind B2 · utility
2Cited by
4References
9Claims
0Family size
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Key dates
| Filing date | Feb 26, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Jun 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for increasing DDR memory bandwidth in DDR SDRAM modules are provided. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued on CAS latency before the completion of the ongoing data burst and the effect of the CAS latency is minimized in terms of the effect on bandwidth. The system and method optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.