Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities
US8688953B2 · kind B2 · utility
7Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Sep 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.