Patent · US Active

System and method for asynchronously and independently controlling core clocks in a multicore central processing unit

US8689037B2 · kind B2 · utility

6Cited by

25References

4Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Bohuslav Rychlik · San Diego, US
Ali Iranli · San Diego, US
Brian J. Salsbery · Superior, US
Sumit Sur · Boulder, US
Steven S. Thomson · San Diego, US
Robert Arthur Glenn · East Leake, GB

Key dates

Filing date	Nov 11, 2010
Grant date	Apr 1, 2014
Priority date	—
Expiry date	Feb 21, 2032

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.