Techniques for embedded memory self repair
US8689081B2 · kind B2 · utility
6Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2011 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | May 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.